High mobility Si1-xGex PMOS transistors to 5K

P-channel Sil-@ex MOSFETs with peak Ge content x =0.3, 0.4, and 0.5 have been fabricated via MBE and experimentally characterized from room temperature down to 5K. Mobility enhancements relative to identically processed Si controls were largest at the lowest tempera2 tures. The highest mobility measured, pm = 1622 cm N.sec for the x = 0.3 SiGe device, was approximately a factor of four higher than the mobility of the Si control devices. Peak mobility decreased as the fraction of Ge in the SiGe channel layer increased for the range of concentrations studied here. P-channel Sil_$ex MOSFETs, which feature a Si substrate / Sil-xGex channel / Si cap layer structure, may be especially interesting for low temperature applications due to their high hole mobilities, reduced SiJSi02 interface scattering and trapping, and potentially steeper subthreshold slopes as compared to Si surface channel devices. Previous work in the MOS area has concentrated on demonstrating the feasibility of such structures (with Ge fraction x 50.3) and reporting mobility results for room temperature operation and perhaps one point in the vicinity of 90K.[1][2][3] Not surprisingly, there has been considerable interest in the SiGe PMOS device, since perhaps this technology might be incorporated into CMOS design, where packing density and circuit speed are limited by the intrinsically poorer PMOS device. Strained SiGe on unstrained Si results in a favorable Type I band lineup, with 97% of the band offset between the smaller gap SiGe and Si occurring in the valence band.[4] The band alignment is favorable for both cryogenic bipolar and MOS design. A SiGe p-type base is ideal for a Si-based npn heterojunction bipolar transistor, since the valence band offset reduces unwanted hole injection back into the emitter, increasing beta, and allows the use of a heavily doped, low resistance base region, resulting in improved high frequency performance. SiGe HBTs have been mentioned as a possible low temperature technology [5] since with higher base doping, beta degradation due to emitter band-gap narrowing and freezeout in the base may be eliminated. In MOS design, the offset in the valence band of the buried SiGe channel sets up a potential well where holes will first accumulate in the buried SiGe layer, then, as the gate voltage is increased, the holes will accumulate at the top Si/SiO2 interface. Higher hole mobilities are a result of the combination of band perturbations in the strained SiGe layer which allow most holes to travel with lower effective mass [6] and a reduction of Si/Si02 interface scattering since hole transport is subsurface. For the same reason, the noise performance of the buried channel devices should also be superior to straight surface channel devices. Operation at cryogenic temperatures should result in very high "bulk-like" hole mobilities, limited by ionized impurity scattering, and to a lesser degree by Si/Si02interface scattering. In this work, we have investigated the performance of high Ge fraction (x = 0.3, 0.4, and 0.5) Sil-fie, channel PMOS transistors at temperatures as low as 5K. Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jp4:1994611 JOURNAL DE PHYSIQUE IV N-type Silicon Substrate